1. Field of the Invention
The present invention relates to a constant voltage generating circuit and particularly to an improvement of a constant voltage generating circuit formed by field effect transistors.
2. Description of the Prior Art
Generally, a constant voltage generating circuit is a circuit for maintaining output voltage constant even if power source voltage is changed. Such a constant voltage generating circuit is shown for example in "An Experimental 1 Mb DRAM with On-Chip Voltage Limiter" by Kiyoo Itoch et al. in ISSCC84, Digest of Technical Papers, page 282. FIG. 1 is a circuit diagram showing a conventional constant voltage generating circuit formed by MOS filed effect transistors (MOS FET's). First, the structure of the conventional constant voltage generating circuit shown in FIG. 1 will be described. In FIG. 1, power supply voltage V.sub.cc is applied to a terminal 1 and constant voltage V.sub.OUT is provided from a terminal 2. The power supply voltage V.sub.cc applied to the terminal 1 is supplied to the source of a p-channel MOS FET 3 and the drain of the p-channel MOS FET 3 is connected to the drain of a n-channel MOS FET 4 and to the output terminal 2 via a node A. The gate of the p-channel MOS FET 3 is grounded. Further, the source of the n-channel MOS FET 4 is also grounded. These MOS FET's 3 and 4 form an output portion of the constant voltage generating circuit, in which the p-channel MOS FET 3 functions as pull-up means for pulling the output voltage to the power supply voltage V.sub.cc and the n-channel MOS FET 4 functions as pull-down means for pulling the output voltage to the grounding potential.
Between the node A of the p-channel MOS FET 3 and the n-channel MOS FET 4 and the grounding potential, n-channel MOS FET's 5 and 6 and a resistor 7 having a resistance value R1 are connected in series. The n-channel MOS FET's 5 and 6 have their gates connected to their drains respectively. A node B2 between the source of the n-channel MOS FET 6 and the resistor 7 is connected to the gate of the n-channel MOS FET 4. These n-channel MOS FET's 5 and 6 and resistor 7 form an output control portion of the constant voltage generating circuit.
Now, description will be given to the operation of the conventional constant voltage generating circuit shown in FIG. 1. The resistance value R1 of the resistor 7 is set to a value considerably higher than a resistance value of the conducted n-channel MOS FET's 5 and 6 and as a result, the n-channel MOS FET's 5 and 6 are stable in a boundary state between the non conductive state and the conductive state. Therefore, the potential V.sub.B1 at a node B1 between the source of the n-channel MOS FET 5 and the drain of the n-channel MOS FET 6 is a value obtained by subtracting the threshold voltage V.sub.THT5 of the n-channel MOS FET 5 from the gate potential of the n-channel MOS FET 5, that is, V.sub.OUT and this value is expressed by the following equation. EQU V.sub.B1 =V.sub.OUT -V.sub.THT5 ( 1)
The potential VB.sub.2 at the node B2 between the source of the n-channel MOS FET 6 and the resistor 7 is a value obtained by subtracting the threshold voltage V.sub.THT6 of the n-channel MOS FET 6 from the gate potential of the n-channel MOS FET 6, that is, V.sub.B1 and is expressed by the following equation. EQU V.sub.B2 =V.sub.B1 -V.sub.THT6 ( 2)
By substituting the equation (1) into the equation (2) to eliminate V.sub.B1, the below indicated equation is obtained. EQU V.sub.B2 =V.sub.OUT -(V.sub.THT5 +V.sub.THT6) (3)
On the other hand, the p-channel MOS FET 3 is always in the conducted state since the gate thereof is grounded, and the impedance thereof is set to a value higher than the impedance of the n-channel MOS FET 4 in the conducted state. However, the impedance of the p-channel MOS FET 3 cannot be made as large as the resistance value R1 of the resistor 7 because the p-channel MOS FET 3 is generally required to drive a large load connected to the output terminal 2. Consequently, the n-channel MOS FET 4 is stable in a slightly conducted state and the gate potential thereof, that is, V.sub.B2 is expressed by the below indicated equation. EQU V.sub.B2 =V.sub.THT4 +.alpha. (4)
where V.sub.THT4 is threshold voltage of the n-channel MOS FET 4 and .alpha. is a value representing a degree of conduction of the n-channel MOS FET 4, this value .alpha. depending on a ratio between the impedance of the p channel MOS FET 3 and the impedance of the n=channel MOS FET4.
By eliminating V.sub.B2 based on the equation (3) and (4), V.sub.OUT is represented as follows. EQU V.sub.OUT =V.sub.THT4 +V.sub.THT5 +V.sub.THT6 +.alpha. (5)
Therefore, as indicated in the equation (5), the output voltage V.sub.OUT is represented as the sum of the threshold voltages of the respective MOS FET's, not depending on the power supply voltage V.sub.cc and constant voltage is generated at the output terminal 2.
However, in order to set a desired output voltage V.sub.OUT in a conventional constant voltage generating circuit thus structured, it is necessary to set threshold voltages of the respective MOS FET's by adjusting the ion implantation amount in the channel portions of the MOS FET's, and using this method, the manufacturing process of a constant voltage generating circuit becomes extremely complicated.
In case where a constant voltage generating circuit is formed only by the MOS FET's all having the same threshold voltage, output voltage V.sub.OUT can be increased or decreased by removing the n-channel MOS FET 5 or 6, or by further providing a MOS FET in series with the n-channel MOS FET's 5 and 6. However, the output voltage in this case is made only an integer multiple of the above stated same threshold voltage and cannot be set to other voltage values.
Further, in such a conventional constant voltage generating circuit thus structured, an absolute value .vertline.V.sub.OUT -V.sub.cc .vertline. of the gate-source voltage of the p-channel MOS FET 3 is increased when the power supply voltage V.sub.cc changes to be high and in consequence, the impedance of the p-channel MOS FET 3 is decreased. More specifically, when the power supply voltage V.sub.cc increases, .alpha. also increases. Accordingly, as is obvious from the equation (5), the output voltage V.sub.OUT depends somewhat on the power supply voltage V.sub.cc and constant voltage cannot be supplied by the constant voltage generating circuit. Such dependency of the output voltage V.sub.OUT on the power supply voltage V.sub.cc is also indicated as the experimental data in the above stated paper written by Kiyoo Itoh et al.